| Copyright | © 2015-2016 Christiaan Baaij 2017 Google Inc. 2019 Myrtle Software Ltd |
|---|---|
| License | Creative Commons 4.0 (CC BY 4.0) (https://creativecommons.org/licenses/by/4.0/) |
| Safe Haskell | None |
| Language | Haskell2010 |
Clash.Examples.Internal
Description
Documentation
upCounter :: forall (dom :: Domain). HiddenClockResetEnable dom => Signal dom Bool -> Signal dom (Unsigned 8) Source #
upCounterLd :: forall (dom :: Domain). HiddenClockResetEnable dom => Signal dom (Bool, Bool, Unsigned 8) -> Signal dom (Unsigned 8) Source #
upDownCounter :: forall (dom :: Domain). HiddenClockResetEnable dom => Signal dom Bool -> Signal dom (Unsigned 8) Source #
lfsrF :: forall (dom :: Domain). HiddenClockResetEnable dom => BitVector 16 -> Signal dom Bit Source #
lfsrGP :: forall (n :: Natural) a. (KnownNat (n + 1), Bits a) => Vec (n + 1) Bool -> Vec (n + 1) a -> Vec (n + 1) a Source #
lfsrG :: forall (dom :: Domain). HiddenClockResetEnable dom => BitVector 16 -> Signal dom Bit Source #
grayCounter :: forall (dom :: Domain). HiddenClockResetEnable dom => Signal dom Bool -> Signal dom (BitVector 8) Source #
oneHotCounter :: forall (dom :: Domain). HiddenClockResetEnable dom => Signal dom Bool -> Signal dom (BitVector 8) Source #
crc :: forall (dom :: Domain). HiddenClockResetEnable dom => Signal dom Bool -> Signal dom Bool -> Signal dom Bit -> Signal dom (BitVector 16) Source #
Constructors
| RxReg | |
Instances
Constructors
| TxReg | |
Instances
| NFDataX TxReg Source # | |||||
Defined in Clash.Examples.Internal | |||||
| Generic TxReg Source # | |||||
Defined in Clash.Examples.Internal Associated Types
| |||||
| type Rep TxReg Source # | |||||
Defined in Clash.Examples.Internal type Rep TxReg = D1 ('MetaData "TxReg" "Clash.Examples.Internal" "clash-prelude-1.8.4-1CKHk9HHRNIGPqhYHQsmcW" 'False) (C1 ('MetaCons "TxReg" 'PrefixI 'True) ((S1 ('MetaSel ('Just "_tx_reg") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 8)) :*: S1 ('MetaSel ('Just "_tx_empty") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 Bool)) :*: (S1 ('MetaSel ('Just "_tx_over_run") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 Bool) :*: (S1 ('MetaSel ('Just "_tx_out") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 Bit) :*: S1 ('MetaSel ('Just "_tx_cnt") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (Unsigned 4)))))) | |||||
uart :: forall {dom :: Domain}. (Hidden "clock" (Clock dom), Hidden "reset" (Reset dom), Hidden "enable" (Enable dom), KnownDomain dom) => Signal dom Bool -> Signal dom (BitVector 8) -> Signal dom Bool -> Signal dom Bit -> Signal dom Bool -> Signal dom Bool -> (Signal dom Bit, Signal dom Bool, Signal dom (BitVector 8), Signal dom Bool) Source #